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Advanced Design Verification Engineer (SystemVerilog)

OMNIVISION
Singapore· Engineering Jobs· 720–1440 July 27, 2026
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VerificationEngineerSystemVerilogAdvancedOMNIVISIONseekingpassionatestateartmethodologiesUVMC++

About the role

OMNIVISION is seeking a Design Verification Engineer to join a passionate verification team, developing state-of-the-art methodologies across UVM, C/C++ co-simulation, system emulation and formal verification. The goal is zero-defect with the best approaches to large verification space. The candidate should have a strong background in Verilog/SystemVerilog and be proficient in programming, with optional experience in CNN/Transformer and NPU/GPU/DSP verification. J-18808-Ljbffr
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