About the role
As a Design Verification Manager, you are expected to carry out the following responsibilities. Be in-charge of a passionate verification team that is constantly pushing the limits – developing and deploying state-of-the-art verification methodologies in ever-increasing design complexities, from UVM, C/C++ co-simulation, system emulation to mixed-mode simulation & formal verification. Conduct thorough test plan reviews systematically and execute the plan on-time with high quality. Achieve zero-…