About the role
We’re looking for someone with strong hands-on experience in ATPG, scan, and DFT flows, with the ability to independently handle DFT tasks and debug complex issues. Must Have: 3 years of SoC/ASIC Digital Design with DFT experience Strong hands-on ATPG experience ATPG coverage analysis and fault coverage improvement ATPG pattern verification using no-timing and SDF-annotated simulations Debugging simulation miscompares and root-cause analysis Knowledge of scan chain insertion and DFT insertion f…