About the role

Cambridge, UK | Full-time | Permanent | Hybrid  Salary: £37,000 - £40,000     About us  Riverlane’s mission is to master quantum error correction (QEC) and unlock a new age of human progress. From advances in material and climate science, to complex chemistry simulation for new drug design, quantum computers will help humanity solve some of its most important challenges. But without QEC, the industry’s defining technical challenge, such breakthroughs can never be achieved.  Riverlane is the world leader in QEC technology. QEC is a complex problem that requires a range of skills, talent and passion.   Having raised more than $125M in funding to date to accelerate our cutting-edge R&D in quantum error correction (QEC), Riverlane partners with many of the world’s leading quantum hardware providers and government agencies to make fault-tolerant quantum computing a reality. We’re making remarkable progress and growing fast.     About the role  We have an exceptional opportunity for a Graduate Verification Engineer to join our talented team of hardware designers and embedded software engineers. Together, you’ll deliver fully verified, high-performance, and trusted systems.    In this exciting role you ll have end-to-end visibility across the entire stack, owning different aspects of verification and shaping how quality and reliability are built into our cutting-edge technology. You do not need a background in quantum computing! You will learn this along the way.    What you will do - specific responsibilities: As a Graduate Verification Engineer at Riverlane, you will:  <ul> <li>Help with developing and executing verification plans for hardware blocks in Quantum Error Correction Systems</li> <li>Learn and support the creation of testbenches using SystemVerilog and UVM</li> <li>Run simulations and perform debugging to resolve issues in collaboration with the design team</li> <li>Collaborate with multi-disciplinary teams to understand specifications and define verification strategies for Quantum Error Correction systems</li> <li>Learn and apply best practices in verification to make methodology improvements</li> </ul>   What we need - Essential Skills/Experience: <ul> <li>Bachelor’s or Master’s degree in Electrical Engineering, Computer Science or related discipline</li> <li>Understanding of Digital Logic Design</li> <li>Some familiarity with HDL languages (e.g. Verilog, SystemVerilog) and simulation tools</li> <li>Good communication and problem-solving skills</li> </ul>   Even better if you have… <ul> <li>Relevant academic projects/internships/work experience</li> <li>Exposure to scripting languages such as Python</li> <li>Understanding of Object-Oriented Programming</li> <li>Exposure to UVM</li> </ul>   What can you expect from us  <ul> <li data-leveltext="" data-font="Symbol" data-listid="22" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1">A comprehensive benefits package that includes an annual bonus plan, private medical insurance, life insurance, and a contributory pension scheme  </li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="22" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="2" data-aria-level="1">Equity, so that our team can share in the long-term success of Riverlane  </li> </ul> <ul