About the role
Bitdeer Technologies Group in Singapore seeks a verification engineer to implement UVM-based verification, SystemVerilog/Verilog, and SVA across RTL designs. You will develop test plans, create stimuli, execute simulations, and debug complex RTL issues. Join a high-impact team leveraging Palladium Z1, HAPS and Zebu platforms, with strong emphasis on coverage, regression, and sign-off readiness in a fast-growing crypto-asset environment. J-18808-Ljbffr